`timescale 1ns/1ns
module sequence_detect(
           input clk,
           input rst_n,
           input data,
           output match,
           output not_match
       );

reg [2: 0] cnt;
reg [5: 0] temp;
always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			begin
				cnt <= 3'd0;
				temp <= 6'd0;
			end
		else if (cnt == 3'd6)
			begin
				cnt <= 3'd1;
				temp <= {temp[4: 0], data};
			end
		else
			begin
				cnt <= cnt + 1'b1;
				temp <= {temp[4: 0], data};
			end
	end

assign match = (cnt == 3'd6) ? (temp == 6'b011100) ? 1 : 0 : 0;
assign not_match = (cnt == 3'd6) ? (temp != 6'b011100) ? 1 : 0 : 0;
endmodule
